Maximizing the amount of parallelism is a conventional technique to increase the performance of an electronic circuit. An electronic circuit performs logic operation on data that is stored in a storage element and produces data that is output to the outside world, or stored in the same or a different storage element. By storing data in several storage elements in parallel, under the constraint that no data-dependency relation exists, processing of these input values can be started in parallel as well.
Such electronic circuits exhibit power consumption peaks when data is stored in a number of storage elements in parallel, and the more storage elements are activated in parallel, the higher the power consumption peak is. A power consumption peak is not only exhibited by the activation of the storage elements, but also by the distribution of the signal to activate the storage elements as well as by the induced effect of the values of the output data changing. These peaks in power consumption may not be affordable in certain applications. For example, in case of mixed signal circuits, where analog or radio frequency elements are integrated near electronic circuits, bouncing of the power supply must be controlled. In case of electronic circuits applied in smart cards, the power consumption peak must be controllable as well, especially during contactless operation in order to control the level of electromagnetic emission.
It is an object of the invention to control the power consumption peaks in electronic circuits.
This object is achieved with an electronic circuit comprising a plurality of storage elements arranged for storing of data elements, and a plurality of processing elements arranged for processing data elements stored in the plurality of storage elements. The storage elements of the plurality of storage elements are further arranged to load their data elements at respective points in time of a first set of points in time, and wherein the points in time are mutually different in order to meet a maximum allowable value of the power consumption peaks. By differing these points in time of respective storage elements, these storage elements are sequentially activated. The corresponding logic circuitry for processing the data elements is therefore sequentially activated as well. By varying the difference in points in time such that a maximum allowable value for the peak in power consumption is not exceeded, the power consumption peaks in electronic circuits are controlled. Furthermore, the voltage of the power supply does not have to be reduced in order to control the power consumption peaks. The invention can be applied for both synchronous electronic circuits as well as for asynchronous electronic circuits. The maximum allowable value in the power consumption peaks depends, amongst others, on the type of electronic circuit and the application of the circuit.
A synchronous electronic circuit for processing data elements is described in an article by Ashok Vittal et al, titled “Clock Skew Optimization for Ground Bounce Control”, Proc. International Conf. Computer-Aided Design (ICCAD), pages 395-399, 1996. Vittal et al describe an approach to reduce the amount of ground bounce in a synchronous circuit. Given a target clock frequency, the amount of ground bounce is minimized, that is, the higher current peaks are lowered as much as possible. It is based on sub-dividing the synchronous clocking into multiple sub-clocks with relative skew, where feasible. This spreads the computation across a large part of the clock cycle instead of largely occuring at the beginning. Their method allows to distribute a single clock that is skewed where possible, so as to make the circuit activity appear more asynchronous, and thus to reduce the power consumption peaks, but all within the timing constraints that still have to be met. Their article does not disclose how to achieve a specified target for the maximum power consumption peaks, i.e. the ground bounce, and then to maximize the performance of the circuit under this condition.
U.S. Pat. No. 6,262,612 describes a digital circuit for processing data stored in storage elements. The storage elements are clocked using a common clock signal, and the clock signal is delayed with a different value for different storage elements. As a result, the supply current peaks are reduced. However, it does not disclose how to achieve a specified target for the maximum power consumption peaks.
U.S. Pat. No. 6,363,007 discloses a method for writing magneto-resistive memory devices to help reduce peak currents during a write. The magneto-resistive memory device has a number of magneto-resistive bits organized into a number of words. All of the magneto-resistive bits in a word are selected by a common word line, and each magneto-resistive bit in a particular word is selected by a different digital line. To write such a memory, a selected one of the word lines is first activated to select all of the magneto-resistive bits in a desired word. Thereafter, the digital lines that correspond to selected magneto-resistive bits in the desired word are sequentially activated. Because the digital lines are sequentially activated, rather than activated in parallel, the peak currents experienced during write operation are reduced. Using this method, a set of bits can be written sequentially to the magneto-resistive memory. However, this document does not disclose a method for the sequential activation of circuit based storage elements, such as flip-flops or latches. It does also not disclose the sequential storage of data blocks having arbitrary number of bits in a memory. Finally, in the document the problem of non-controllable power consumption peaks in relation to the application of a memory or electronic circuit is not discussed.
An embodiment of the invention is characterized in that the electronic circuit further comprises a clock generator arranged to generate periodic clock signals, and delay elements arranged to generate a point in time of the first set for a respective one of the storage elements by adding respective delays to a source clock signal, wherein the respective delays are mutually different, and wherein the frequency of the clock generator is low enough in order to ensure data integrity during processing of the data elements. In general, a synchronous electronic circuit allows to obtain a high performance by optimizing the timing behaviour of the circuit. However, by storing data elements in the storage elements in parallel, the resulting power consumption peaks may be too high for a particular application. By applying the proper delays to the clock signal, the power consumption peaks can be controlled. The clock frequency is kept low enough in order to ensure data integrity during operation of the electronic circuit. However, the loss in performance is outweighed by the reduction in the power consumption peaks below a maximum allowable value.
An embodiment of the invention is characterized in that the electronic circuit further comprises a timing circuit arranged to determine the first set of points in time in a first operating mode, wherein the timing circuit is further arranged to determine a second set of points in time, in a second operating mode, at which respective storage elements of the plurality of storage elements load their data elements, wherein the respective points in time of the second set of points in time are essentially identical, and wherein the timing circuit is further arranged to select an operating mode depending on a control signal. Using the control signal, the storage elements can be activated either in parallel or sequentially, allowing to use the trade off between controlling the power consumption peaks and maximizing the performance of an electronic circuit.
An embodiment of the invention is characterized in that the timing circuit comprises a first clock generator arranged to generate periodic clock signals, each to determine the respective points in time of the first set of points in time, and wherein the timing circuit further comprises a second clock generator arranged to generate periodic clock signals, each to determine the respective points in time of the second set of points in time. Using two different clocks is a relatively simple way to generate the two sets of points in time in a synchronous circuit. The frequency of the second clock generator may be reduced, compared to the frequency of the first clock generator, in order to ensure data integrity during operation of the electronic circuit.
An embodiment of the invention is characterized in that the electronic circuit further comprises delay elements arranged to generate a point in time of the first set for a respective one of the storage elements by adding respective delays to a source clock signal, wherein the respective delays are mutually different. Delaying the clock signal is a relatively simple way of generating different points in time in a synchronous circuit.
An embodiment of the invention is characterized in that the timing circuit comprises a clock generator arranged to generate periodic clock signals, each to determine the respective points in time of either the first set of points in time or the second set of points in time, depending on the control signal. An advantage of this embodiment is that only one clock generator is required, for generating either the points in time of the first set or the second set.
An embodiment of the invention is characterized in that the electronic circuit is a self-timed circuit, further comprising a handshake channel arranged for communication between storage elements of the plurality of storage elements and processing elements of the plurality of processing elements, and delay elements arranged to generate a point in time of the first set for a respective one of the storage elements by adding respective delays to a request signal for loading of the data elements, wherein the delays are mutually different. Delaying the request signal is a relatively simple way of implementing mutually different points in time for the storage elements. An advantage of self-timed circuits is that data are exchanged using a handshake to indicate the validity and acceptance of data, in general resulting in lower power consumption when compared to synchronous electronic circuits.
An embodiment of the invention is characterized in that the electronic circuit is a self-timed circuit, further comprising handshake channels arranged for communication between storage elements of the plurality of storage elements and processing elements of the plurality of processing elements, and a first handshake component arranged to receive a request signal, in a first operating mode, for loading of data elements and in response thereto to generate a request signal for a respective one of the storage elements of the plurality of storage elements for loading of data elements at respective points in time of the first set of points in time. An advantage of this embodiment is that a single handshake component allows to sequentially activate several storage elements.
An embodiment of the invention is characterized in that the electronic circuit further comprises a second handshake component arranged to receive a request signal, in a second operating mode, for loading of data elements and in response thereto to generate a request signal for a respective one of the storage elements of the plurality of storage elements for loading of data elements, wherein the request signals are generated at essentially identical points in time, and wherein the electronic circuit is further arranged to select an operating mode depending on a control signal. Using the control signal, the storage elements can be activated either in parallel or sequentially, allowing to use the trade off between reducing the power consumption peaks and increasing the performance of a self-timed electronic circuit.
According to the invention, a method of processing data elements comprises: determining a first set of points in time, in a first operating mode, for storing data elements in respective storage elements of a plurality of storage elements, and generating output data elements each by performing respective logic operation on respective data elements, wherein the points in time of the first set of points in time at which respective storage elements load their data elements are mutually different in order to meet a maximum allowable value of the power consumption peaks. Power consumption peaks are controlled as a result of the sequential activation of the storage elements. An eventual loss in performance is acceptable and outweighed by the reduction of the power consumption peaks below a maximum allowable value.
An embodiment of the invention is characterized in that the method further comprises: determining a second set of points in time, in a second operating mode, for storing data elements in respective storage elements of the plurality of storage elements, wherein the points in time of the second set of points in time at which respective storage elements load their data elements are essentially identical, and selecting an operating mode, depending on a control signal. An advantage of this embodiment is that it allows to use the trade off between controlling the power consumption peaks and maximizing the performance of an electronic circuit.